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Generation

So I finished the verification generator and it seems to run pretty well, and validates on RARS.

When experimenting with MUL I found that Jupiter isn't actually generating the right mnemonics, I'm not entirely sure what's going on, if it's generating RV64i equivalents - doesn't seem to be.But for things like ADD the upper 7 bits are zero and they're not. Probably make sense when I get further into RISC V.

Then I wrote a fairly standard emulator generator that produces C. I reduced the basic opcode to 256 ; every rv32i opcode ends in 11, so that's 5 bits from that and 3 function bits. This way I can make the code generator in the case statement use a jump vector table rather than some lookup nonsense.

Next up is to get the 'C' code verified, then build that into something resembling an emulator.

L8R: I have the generated C code compiling and most of the support code written. Should get some code running in C, including the verifier hopefully tomorrow.

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