Even though the CPU is relatively simple, I still want to verify it. I've got two Java emulators, which seem to work okay .... ish. One seems to be more established and supported (RARS) so I will verify against that.
Jupiter has the option to dump code and data so it can operate as an assembler, so I use that to generate object code (a text file of hex constants, but it'll do)
So Plan 9 is to write some Python scripts to generate verification code using a seeded RNG, so I can reseed it if there's a problem. I've got a skeleton so far, but no actual code in it, yet. Then I'll write a reference emulator in Python to check I understand how the RV32I instructions work, which look relatively straightforward.
Then I'll write a proper emulator in C, verify that, and start on the design and implementation of the quasi-assembler.
L8R: I have a Python emulator that mostly seems to work .... it probably doesn't :( only missing the load and store instructions which will be done tomorrow.
Then I will start work on the verification of the various instruction groups, testing it against the RARS emulator then the Python emulator. Once this is done I can be reasonably confident in the implementation. RARS is used by many university courses so any significant bugs should have been picked up.
The only tricky thing about writing a rv32i emulator is the messy opcodes the Branch and Jump and SB/SH/SW opcodes have.
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